Improving Energy Efficiency in Loop Pipelining by Rational-II Modulo Scheduling
dc.contributor | {"last":"Sittel","first":"Patrick","affiliation":"Sartorius","role":"Other"} | |
dc.contributor | {"last":"Zipf","first":"Peter Prof. Dr.","affiliation":"Fachgebiet Digitaltechnik","role":"Other"} | |
dc.contributor.author | {"last":"Fiege","first":"Nicolai","affiliation":"Fachgebiet Digitaltechnik"} | |
dc.date.accessioned | 2022-04-08T14:32:15Z | |
dc.date.available | 2022-04-08T14:32:15Z | |
dc.date.Submitted | 11.04.2022 | |
dc.identifier.uri | https://daks.uni-kassel.de/handle/123456789/44 | |
dc.identifier.uri | http://dx.doi.org/10.48662/daks-10 | |
dc.description | This data set contains the full experimental data we analyzed for the publication "Improving Energy Efficiency in Loop Pipelining by Rational-II Modulo Scheduling" published at International Symposium on Field-Programmable Custom Computing Machines (FCCM) 2022. | de_DE |
dc.language.iso | eng | de_DE |
dc.rights.uri | https://rightsstatements.org/page/InC/1.0/ | |
dc.subject | High-Level Synthesis | de_DE |
dc.subject | Energy efficiency | de_DE |
dc.subject | Scheduling | de_DE |
dc.subject.classification | 409-07 Rechnerarchitekturen und eingebettete Systeme | de_DE |
dc.subject.ddc | 004 | |
dc.title | Improving Energy Efficiency in Loop Pipelining by Rational-II Modulo Scheduling | de_DE |
dc.type | Dataset | de_DE |
local.ka.faculty | FB16:Elektrotechnik/Informatik | de_DE |
local.ka.department | Digitaltechnik | de_DE |
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